Computer System Architecture - Microprogrammed Control
- Option : A
- Explanation : The 7 mutually exclusive signals can be encoded in ceiling(log2 7) = 3 bits,
while the remaining 13 signals will remain un-encoded. So the number of
bits in a control word will be 3 + 13 = 16.
- Option : A
- Explanation : For horizontal encoding, one bit is used for each control signal; therefore, we shall require 126 control signals.
For vertical encoding, the 126 control signals can be encoded in ceiling(log2 126) = 7 bits.
18. Which of the following is true for MIPS32 register bank?
- Option : C
- Explanation : In MIPS32 architecture, two register operands are prefetched during the ID stage, which required two read ports in the register bank. Also, for pipelined implementation, a register write can occur during WB. Thus two read and one write ports are required in the register bank.
19. Which of the following is true for the ID(Instruction Decode) stage of the MIPS32 data path?
- Option : A
- Explanation : Option A and B both are correct.
For the MIPS32 instruction execution, the instruction is decoded and the register operands are pre-fetched during ID stage.
