Computer System Architecture - Microprogrammed Control

6. The 4 micro-operations of an instructions fetch cycle are shown below.
Which of the following clock cycle groupings are possible?

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7. The block diagram of a CPU with single bus organization is given below.

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Which of the following control steps are required to execute the instruction “ST R1, 32” (store the content of R1 at memory location 32)?

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8. The first three steps used to fetch the instructions "ADD R1,R2" (in the CPU with single bus organization shown in question 7) are given below
1. PCout , MARin, Read, Select=0, Add, Zin
2. Zout , PCin , WMFC
3. MDRout, IRin

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The values in the PC, MAR, MDR and IR after Step 1 and Step 2 are shown above. What are the values of PC, MAR and IR after Step 3?

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9. What is the 6th control step involved in completely executing the instructions "ADD R1,R2" (in the CPU with single bus organization shown in question 7)?
1. PCout , MARin, Read, Select=0, Add, Zin
2. Zout , PCin , WMFC
3. MDRout, IRin
4. R2out, Yin
5. R1out, Select=1, Add, Zin
6.____________________

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10. Which of the following statements are true for horizontal micro- instruction encoding?

  • Option : A.B
  • Explanation : In horizontal microinstruction encoding, there is one separate bit for every control signal. Hence any number of control signals can be activated simultaneously.
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