PREVIOUS YEAR SOLVED PAPERS - July 2016 Paper 3

Avatto > > UGC NET COMPUTER SCIENCE > > PREVIOUS YEAR SOLVED PAPERS > > July 2016 Paper 3

Option : D
Explanation :
8085 microprocessor has 5 hardware interrupts. Named TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. 8086 microprocessor has 2 hardware interrupts. Named NMI and INTR. So, option (D) is correct.

Option : A
Explanation :
DAD will perform Double addition (16 bit) between HL pair and any other pair of register. Among HL, BC, DE and SP; B, H and D register will be used first. So, DAD H will do HL = HL + HL; DAD B will do HL = HL + BC; DAD D will do HL = HL + DE; SP is stack pointer and it is not a pair register, DAD SP will do HL = HL + SP; So, option (A) is correct.

Option : C
Explanation :
The register that stores all interrupt requests is Interrupt request register.
Interrupt mask register is a read and write register. This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.
Interrupt service register handle the interrupt and service them according to priority and other condition.
Status register is a hardware register that contains information about the state of the processor

Option : D
Explanation :
The displacement addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.
Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.
Based Indexed plus displacement addressing mode: In this mode of addressing the operand’s offset is given by offset=[BX or BP]+[SI or DI]+8 bit or 16 bit displacement.
Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI or DI and an 8 bit or 16 bit displacement.