Pipeline and Vector Processing Q.15

0. Consider an instruction pipeline with five stages without any branch prediction : Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instruction I1, I2, I3, ........... I12 is execute in the pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

Answer
Comment
Array

Option : A
Explanation : Given: Five stage instruction pipeline Delays for FI, DI, FO, EI and WO are 5, 7, 10, 8, 6 ns resp.
To find: Time needed to execute 12 instruction prog.
Analysis: Since the max. time taken by any stage is 10 ns and additional 1 ns is required for delay of buffer. Therefore total time for an instruction to pass from one stage to another is 11ns. Now instructions are executed as follows:
Now when I₄ is in its execution stage we detect the branch and when I₄ is in WO stage we fetch I₉ so time for execution of instructions from I₁ to I₄ is = 11*5 + (4 – 1)*11 = 88 ns.
And time for execution of instructions from I₉ to I₁₂ is = 11*5 + (4 – 1)*11 = 88 ns. = 88 ns. But we have 11ns when fetching I₉ i.e. I₉ requires only 44 ns additional instead of 55 ns because time for fetching I₉ can be overlap with WO of I₄.
Hence total time is = 88 + 88 – 11 = 165 ns

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