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0. The block diagram of a CPU with single bus organization is given below. Which of the following control steps are required to execute the instruction “ST R1, 32” (store the content of R1 at memory location 32)?
1. IRout, MARin 2. MDRin, R1out, Write 3. MDRout, WMFC
1. WMFC 2. IRout, MARin, Write 3. MDRout, R1in
1. WMFC 2. MDRout, R1in 3. IRout, MARin, Write
1. IRout, MARin, Read 2. MDRin, WMFC 3. MDRout, R1in
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