Microprogrammed Control Q.18
0. Which of the following is true for MIPS32 register bank?
- Option : C
- Explanation : In MIPS32 architecture, two register operands are prefetched during the ID stage, which required two read ports in the register bank. Also, for pipelined implementation, a register write can occur during WB. Thus two read and one write ports are required in the register bank.
