Memory Hierarchy Q.68
Consider a machine a 2-way set associative data cache
of size 64 Kbytes and block size 16 bytes. The cache is
managed using 32 bit virtual addressed and the page
size is 4 Kybytes. A program to be run on this machine
begins as follows :
double APR {1024] [1024]
int i, j ;
/ * Initalize array APR to 0.0*/
for (i = 0; i < 1024; i ++)
for (j = 0; j < 1024; j++
APR [i] [j] = 0.0;
The size of double 8 bytes. Array APR is memory
starting at the beginning of virtual page 0 × FF000
and stored in row major order. The cache is initially
empty and no pre-fetching is done. The only data
memory references made by the program are those to
array APR.
0. The total size of the tags in the cache directory is
- Option : D
- Explanation : Virtual Address = 32 bits
Cache address is divided into TAG, SET, BLOCK
For BLOCK of 16 bytes, we need 4 bits.
Total number of sets(each set containing 2 Blocks)
= 64 KB/(2 * 16) B = 211
So, Number of SET bits = 11
Number of TAG bits = 32 – (11 + 4) = 17
So, cache address = 17 |11| 4 (TAG |SET| BLOCK)
Tag memory size
= Number of tag bits * Total number of blocks
= 17 * 2 * 211 (Total Number of blocks
= 2 * Total number of sets)
= 68 KB
