Memory Hierarchy Q.35
A CPU has a 32 KB direct mapped cache with 28-byte block size. Suppose A is a two dimensional tray of size 512 × 512 with elements that occupy 8-bytes each. Consider the following two C code segments P1 and P2
P1 : for (i = 0, i < 512; i++) {
for (j = 0, j < 512; j++) {
x+ = A [i] [j];
}
}
P2 : for (i = 0, i < 512; i++) {
for (j = 0, j < 512; j++) {
x+ = A [i] [j];
}
}
P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2
- Option : C
- Explanation : [P2] runs the loops in a way that access elements of A in r ow major order and [P2] accesses elements in column major order.
No of cache blocks = Cache Size/Block Size
= 32KB / 128 Byte = 256
No. of array elements in Each Block
= Block Size/Element Size
= 128 Byte / 8 Byte = 16
Total Misses for [P1] = ArraySize * (No. of array elements in Each Block) / (No of cache blocks) = 512 * 512 * 16/256
= 16384
