Memory Hierarchy Q.30

0. A CPU has a 32 kB direct mapped cache with 128-byte block size. Suppose A is a two dimensional array of size 512 x 512 with elements that occupy 8-bytes each. Consider the following two C code segments, Pl and P2
P1 : for (i=0; i<512; i++ ) {
for (j=0; j<512; j++) {
X+ = A[i] [j];
}
}
P2 : for(i=0; i<512; i++) {
for (j=0 ; j< 512; j ++) {
{X+ = A[j] [i];}
}
}
P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M₁ and that for P2 be M₂.

The value of the ratio M₁/M₂ is

Answer
Comment
Array

Option : B
Explanation : When A [0] [0] is accessed, block from A [0] [0] to A [0] [15] is brought into the cache but it is of no use as the next element required to access will be A [1] [0].
Thus there will not be a single hit and all 512.512 = 262144 accesses will be misses.
∴ M1 / M2 = 16384/262144 = 1/16

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