Central Processing Unit Q.16
A pipelined processor uses a 4-stage instruction pipeline with the following stages : Instruction fetch (IF), Instruction decode (ID), Executive (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S – R* (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
- Option : C
- Explanation : Read After Write:
1. ADD ⇾ MUL (because of R5)
2. MUL ⇾ SUB (because of R6)
3. SUB ⇾ DIV (because of R5)
4. DIV ⇾ STORE (because of R6)
Write After Read
1. MUL ⇾ SUB (because of R5)
2. DIV ⇾ STORE (because of R6)
Write After Write
1. ADD ⇾ SUB (because of R5)
2. MUL – DIV (because of R6)
