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51. For the circuit shown for AB = 00, AB = 01, C, S values respectively are
0 , 0 and 0, 1
0, 0 and 1, 0
0, 1 and 0, 0
1, 0 and 0, 0
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52. What logic gate is represented by the circuit shown below?
NAND
NOR
AND
EQUIVALENCE
53. The circuit shown below is the
Full adder
Full subtractor
Parity checker
None of these
54. In the following gate network which gate is redundant?
Gate no. 1
Gate no. 2
Gate no. 3
Gate no. 4
55. The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent?
NOT
OR
XOR
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