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Pipeline and Vector Processing Q.23

0. Consider the following data path of a simple non- pipelined CPU. The registers A, B, A1 , A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2 : 1) and the DEMUX is of size 8 × (1 : 2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Data Register). SP can be decremented locally.

pipelining

The CPU instruction “push r”, where r = A or B, has the specification
M[SP] ⇽ r
SP ⇽ SP – 1
How many CPU clock cycles are needed to execute the ‘push r” instruction?

  • Option : A
  • Explanation : Push ‘r’ consist of following operations :
    M[SP ]!R
    SP!SP-1
    ‘r’ is stored at memory at address stack pointer currently is, this take 2 clock cycles
    SP is then decremented to point to next top of stack
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