Central Processing Unit Q.19

19Consider a pipelines processor with the following four stages
IF : Instruction Fetch
ID : Instruction Decode and Operand Fetch
Ex : Executive
WB : Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instruction need 1 clock cycle and the MUL instruction need 3 clock cycles in the Ex stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

central-processing

Option : B
Explanation : For each of the three instruction four stages will be there. Since ,it is a pipelined processor, so one instruction may be fetched while other is being decoded or executed or written back action performed in each clock cycle may be represented as

Only, two instructions cannot be executed simultaneously.

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