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Central Processing Unit Q.1

0. For a pipelined CPU with a single ALU, consider the following situations
1. The j + 1st instruction uses the result of the jth instruction as an operand
2. The execution of a conditional jump instruction
3. The jth and j + 1st instructions require the ALU at the same time
Which of the above can cause a hazard ?

  • Option : D
  • Explanation : (i) j + 1st instruction uses result of the jth instruction as an operand, then read-after- write (RAW) hazard occurs. It is a part of data dependency.
    (ii) Execution of a conditional jump instruction causes a flushing so conditional dependency occurs.
    (iii) jth and j + 1st instructions require the ALU at the same time causes write-after-read (WAR) hazard.
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