Memory Hierarchy Q.69
Consider a machine a 2-way set associative data cache
of size 64 Kbytes and block size 16 bytes. The cache is
managed using 32 bit virtual addressed and the page
size is 4 Kybytes. A program to be run on this machine
begins as follows :
double APR {1024] [1024]
int i, j ;
/ * Initalize array APR to 0.0*/
for (i = 0; i < 1024; i ++)
for (j = 0; j < 1024; j++
APR [i] [j] = 0.0;
The size of double 8 bytes. Array APR is memory
starting at the beginning of virtual page 0 × FF000
and stored in row major order. The cache is initially
empty and no pre-fetching is done. The only data
memory references made by the program are those to
array APR.
- Option : B
- Explanation : ARR[0][0] i s located at virtual address 0xFF000000. Here FF000 is page address and 000 is page offset. So, index bits are 00000000000 Address of ARR[4][0] = 0xFF000 + 4 * 1024* size of (double) [since we use row major storage] = 0xFF000000 + 4096 * 8 = 0xFF000000 + 0x8000 = 0xFF008000 ( index bits matches that of ARR[0][0] as both read 00000000000)
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