Memory Hierarchy Q.41

41A computer system has a level-1 instruction cache (1-cache), a level-1 data cache (D-cache) and a level-2 cache (L2-cache) with the following specifications

	Capacity	Mapping method	Block size
1-cache	4K words	Direct mapping	4 Words
D-cache	4K words	2-way set associative mapping	4 Words
1, 2-cache	64K words	2-way set- associative mapping	16 Words

Capacity Mapping method Block size 1-cache 4K words Direct mapping 4 Words D-cache 4K words 2-way set-associative mapping 4 Words L2 cache 64K words 4-way set-association mapping 16 Words The length of the physical address of a word in the main memory is 30 bits. The capacity of the tag memory in the 1-cache D-cache and L2-cache is, respectively,

Option : A
Explanation : 1. I-cache
Number of blocks in cache = 4K/4 = 210 blocks.
Bits to represent blocks = 10
Number of words in a block = 4 = 22 words.
Bits to represent words = 2.
tag bits = 30 – (10 + 2) = 18.
Each block will have it's own tag bits.
So total tag bits =1K * 18 bits.
2. D-cache
Number of blocks in cache = 4K/4 = 210 blocks.
Number of sets in cache = 210/2 = 29 sets.
Bits to represent sets = 9.
Number of words in a block = 4 = 22 words.
Bits to represent words = 2
tag bits = 30 – (9 + 2) = 19
Each block will have it's own tag bits.
So total tag bits = 1K * 19 bits.
3. L2 cache
Number of blocks in cache = 64K/16 = 212 blocks.
Number of sets in cache = 212/4 = 1024 sets.
Bits to represent sets = 10
Number of words in cache = 16 = 24 words.
Bits to represent words = 4.
tag bits = 30 – (10 + 4) = 16
Each block will have it's own tag bits.
So total tag bits = 212 * 16-bits = 4K * 16-bits.

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