Memory Hierarchy Q.36
A CPU has a 32 KB direct mapped cache with 28-byte block size. Suppose A is a two dimensional tray of size 512 × 512 with elements that occupy 8-bytes each. Consider the following two C code segments P1 and P2
P1 : for (i = 0, i < 512; i++) {
for (j = 0, j < 512; j++) {
x+ = A [i] [j];
}
}
P2 : for (i = 0, i < 512; i++) {
for (j = 0, j < 512; j++) {
x+ = A [i] [j];
}
}
P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2
0. The value of the ratio M1 /M2 is
- Option : B
- Explanation : Total Misses for [P1] = ArraySize * (No. of array elements in Each Block) / (No of cache blocks)
= 512 * 512 * 16 / 256 = 16384
Total Misses for [P2] = Total Number of elements in array (For every element, there would be a miss)
= 512 * 512 = 262144.
Ration M1/M2 = 16384 / 262144 = 1/16.
