Gate2017 ss Q44

44In a two-level cache system, the access times of L₁ and L₂ 1 and 8 clock cycles, respectively. The miss penalty from the L₂ cache to main memory is 18 clock cycles. The miss rate of L₁ cache is twice that of L₂. The average memory access time(AMAT) of this cache system is 2 cycles. The miss rates of L₁ and L₂ respectively are:

Option : A
Explanation :
--Access time of L₁ = 1
--Access Time of L₂=8
--miss penalty L₁ cache (2*L₂) = 18*2 = 2*a
--miss penalty L₂ cache say a = 18
--AMAT (average memory access time) =2
AMAT = Access time of L₁ + (MissRate L₁ * miss penalty L₁) where miss penalty L₁ = Access time of L₂ + (MissRate L₂ * miss penalty L₂)
2 = 1+ 2*a *(8 + a* 18)
Solving the equation,
a=0.111

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