Memory Hierarchy Q.34

34A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c-byte chunks are mapped on consecutive banks with warp-around. All the k banks can be assessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns. The latency of one bank access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is

Option : D
Explanation : The main memory consists of 24 banks, each of 2 bytes. Since parallel accesses t o all banks are possible, only two parallel accesses of all banks are needed to traverse the whole data.
For one parallel access,
Total time = Decoding Time + Latency Time
= 24/2 + 80
= 92ns
Hence, for 2 such accesses,
time = 2 * 92
= 184 ns

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