Gate2017 cs Q50

50Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. Conflict misses are those misses which occur due the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks.
(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129) is repeated 10 times. The number of conflict misses experienced by the cache is __________.

Option : B
Explanation :
A miss is not considered a conflict miss if the block is accessed for the first time.
1st round: (2+2) misses
2nd round: (4+4) misses
∴Total = 4 + (8 × 9) = 76 conflict misses

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