Gate2018 cs Q63

0. The size of the physical address space of a processor is 2^P bytes. The word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size of each cache block is 2^M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

Answer
Comment
Array

Option : B
Explanation :
MM space = 2^P bytes
Physical Address (PA) size = P bits
CM size = 2^N bytes
Block size 2^M words
2^M words*2^W bytes/word
2^M+W bytes
Number of lines = (CM size)/Block size ⇒ 2^N/(2^M+W)
⇒ 2^N-M-W
Number of sets = (Number in cm)/P-way
= 2^N-M-W/K
The Address format

⇒ (N-M-W-log₂K)
∴ Tag size
⇒ P-(N-M-W-log₂K)
⇒ P-N+log₂K)

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