Classical

Computer Organization Architecture - Cache and main memory

26:  

If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits

A.

13

B.

14

C.

16

D.

17

 
 

Option: D

Explanation :

As there are 4*6 = 24 chips so (as  2>= 24 ) 5 bits are required to address them.
in each RAM  number of bytes=(8k*4)/8 = 4k
So to  represent 4k we need(as 212=4096) 12 bits
Therefore  to represent total structure we need 12+5=17 bits.

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sonam said: (8:57pm on Sunday 7th April 2013)
how yoy got this pleas explain

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27:   Four memory chips of 16 x 4 size have their address bases connected together. The system will be of size
A. 64 x 64
B. 16 x 16
C. 32 x 16
D. 256 x I
 
 

Option: B

Explanation :

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28:   How many addresses are required for 25 x 40 video RAM
A. 1020
B. 1900
C. 1000
D. 2000
 
 

Option: C

Explanation :

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29:   Which of the following statements is true ?
A. ROM is a Read / Write memory
B. PC points to the last instruction that was executed
C. Stack works on the principle of LIFO
D. All of above
 
 

Option: C

Explanation :

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30:  

A CPU has a 32 kB direct mapped cache with 128-byte block size. Suppose A is a two dimensional array of size 512 x 512 with elements that occupy 8-bytes each. Consider the following two C code segments, Pl and P2
P1 : for (i=0; i<512; i++ ) {
for (j=0; j<512; j++) {
X+ = A[i] [j];
}
}
P2 : for(i=0; i<512; i++) {
for (j=0 ; j< 512; j ++) {
{X+ = A[j] [i];}
}
}

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.

The value of the ratio M1/M2 is

A.

0

B.

1/16

C.

1/8

D.

16

 
 

Option: B

Explanation :

When A [0] [0] is accessed, block from A [0] [0] to A [0] [15] is brought into the cache but it is of no use as the next element required to access will be A [1] [0].
Thus there will not be a single hit and all 512.512 = 262144 accesses will be misses.
M1 / M2 =  16384/262144 = 1/16

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