When a cache is 10 times faster than main memory , and cache can be used 90% of the time , how much speed we gain by using cache ?
Solution
Let M = Main memory access Time
C= Cache memory access time =M/10 (given)
Total access time using Cache=0.9+0.1 M
=0.9(M/10)+0.1M=0.19M
Speed up= (M/0.19M) 5.3
Consider a CRT display that has a next mode display format of 80x25 characters with a 9x12 character cell. what is the video buffer RAM for the display to be used in monochrome (1 bit per pixel) graphics mode ?
Solution
Number of bits required = Number of characters x cell size
= 80x25x9x12=216000bits
Size of RAM=27000 bytes
Consider the unpipelined machine with 10ns clock cycles. It uses four cycles for ALU operations and branches where as five cycles for memory opeartions. Assume that the relative frequencies of these operations are 40%,20% and 40% respectively. Let due to clock skew and set up pipelining, the machine adds 1 ns of overhead to the clock. How much speed in instruction execution rate will we gain from pipeline ?
Solution
Average instruction execution time = Clock cycle x Average CPI
= 10 ns x [(40%+20%) x 4+40%x5]
= 10ns x 4.4 =44ns
In the pipelined implementation , clock must run at the speed of slowest stage plus overhead , which wil be 10+1=11 ns; this is avarage instruction execution time.
Thus speed up from pipelining ,
( Speed up)Pipelining = Average instruction time unpipelined / Average instruction time pipelined
= 44ns/11ns = 4 times
Assume that the time required for the five functional units , which operate in each of the five cycles are :
10 ns, 8 ns,10 ns,10 ns and 7 ns
Assume that pipelining adds 1 ns of overhead . Find the speed up versus single cycle data path.
Solution
Since unpipelined machine executed all instructions in a single clock cycle,its average time per instruction is simply the clock cycle, its average time per instruction is simply the clock cycle time. The clock cycle time is equal time is equal to sum of the times for each step in execution.
Average instruction execution time = 10+8+10+10+7
= 45 ns
Clock cycle time on pipelined machine must be largest time for any stage in pipeline(10ns) plus overhead of 1 ns, for a total of 11ns.
Since CPI is 1, this yields an average instruction execution time of 11ns.
∴ Speed from pipelining = (Avarage instruction time unpipelined)/ Average instruction time Pipelined
= 45ns/11ns=4.1 times
Consider the multiplication of two 40x40 matrices using a vector processor.
a) how many product terms are there in each inner product, and how many inner products must be evauated ?
b) How many multiple add operations are needed to calculate the product matrix ?
Solution
a) There are 40 product terms in each inner product
402= 1600 inner product must be evaluated, one for each element of the product matrix.
b) 403= 64,000
Consider a computer with four floating point pipeline processors. Let each processor uses a cycle time of 40ns . How long will it take to perform 400 floating point operations ? is there a difference if same 400 opeartions are carried out using a single pipeline processor with a cycle time of 10ns ?
Solution
Divide 400 operations in to 4 processors
Processing time =(400/4) x100 =4000 nsec
Using a single pipeline, processing time = 400x10=4000 nsec
